1. Field of the Invention
The present invention relates to semiconductor devices and design methods thereof and, more particularly, to layout of electrical wiring lines.
2. Description of the Related Art
Semiconductor devices have a structure in which an interlayer dielectric film and a wiring line are stacked or multilayered above a semiconductor substrate in which field effect transistors are formed. Conventionally, a plasma and/or an electron beam is utilized for fabrication of such semiconductor devices. The plasma is utilized, for example, in cleaning processes and in interlayer dielectric film formation processes using plasma CVD. The electron beam is utilized for exposure of a resist which becomes a mask upon patterning of an interlayer dielectric film and/or an electrical conductive film that becomes a wire.
It is inevitable that electrical wires are exposed on or above a semiconductor substrate in the manufacturing process of a semiconductor device. An exposed wire undesirably functions as an antenna for collecting charged particles residing in either a plasma or an electron beam. Since the wire is connected to the gate electrode of a field effect transistor, the charged particles travel through the wire toward the gate electrode, whereby it becomes a problem that a gate insulating film receives damages. This is the so called charge-up damage problem. This damage appears as a change in characteristics of the field effect transistor (such as Vth, Gm, S-factor, Ig or the like).
Here, a ratio of the area of a wire to the gate area of a gate electrode is called the antenna ratio. If the area of the wire is large, that is, if the antenna ratio is significant, then the number of charged particles gathered increases; thus, the gate insulation film becomes more easily affectable by the charge-up damage. Hence, it becomes impossible to unlimitedly enlarge the area (length) of any wire. This means a limitation or constraint relative to the degree of freedom of layout of wires.
When the semiconductor device is designed to employ multilayer wiring technologies, the area (length) of a wire becomes larger, resulting in that the charge-up damage problem becomes more serious. Explaining a plasma as an example, one prior known approach to suppressing the chargeup damage is to improve the performance of semiconductor manufacturing apparatus and/or fabrication processes. More precisely, there are methods for improving the uniformity of a plasma, adjusting the step of an applied voltage, and adjusting a gas or pressure or else (for example, see JP-A-11-8224).